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| HCF4022B OCTAL COUNTER WITH 8 DECODED OUTPUTS s s s s s s s s MEDIUM SPEED OPERATION : 10 MHz (Typ.) at VDD = 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4022BEY HCF4022BM1 T&R HCF4022M013TR DESCRIPTION The HCF4022B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4022B is 4-stage Johnson counter having 8 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. This counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advanced via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson decade-counter configuration permits high speed operation, 2-input decimal decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY - OUT signal completes one cycle every 8 clock input cycles and is used to ripple-clock the succeeding device in a multi-device counting chain. PIN CONNECTION September 2001 1/11 HCF4022B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 2, 1, 3, 7, 11, 4, 5, 10 6, 9 14 13 15 12 8 SYMBOL 0 to 7 NC CLOCK CLOCK INHIBIT RESET CARRY OUT VSS NAME AND FUNCTION Decoded Output Not Connected Clock Input Clock Inhibit Input Reset Input Carry Output Negative Supply Voltage TRUTH TABLE FUNCTIONAL DIAGRAM CLOCK X L X CLOCK INHIBIT X X H L L H H X : Don't Care Qn : No Change RESET H L L L L L L DECODED OUTPUT Q0 Qn Qn Qn+1 Qn Qn Qn+1 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 HCF4022B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C 3/11 HCF4022B DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit IL Quiescent Current A VOH High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current VOL VIH VIL IOH IOL Output Sink Current Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 V V V V mA mA A pF II CI Any Input Any Input The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/11 HCF4022B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns) Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 325 135 85 300 125 80 100 50 40 5 10 11 100 45 30 unlimited 115 50 35 265 115 85 130 55 30 200 140 75 230 100 75 530 230 170 260 110 60 400 280 150 Max. 650 270 170 600 250 160 200 100 80 5 Unit CLOCKED OPERATION tPLH tPHL Propagation Delay Time (decode out) Propagation Delay Time (carry out) tTHL tTLH Transition Time (carry out or decoded out lines) fCL (1) Maximum Clock Input Frequency Minimum Clock Pulse Width Clock Input Rise or Fall Time Data Setup Time Minimum Clock Inhibit ns ns ns 2.5 5 5.5 MHz 200 90 60 tW ns tr , tf s tsetup ns RESET OPERATION tPLH, tPHL Propagation Delay Time (carry out or decoded out lines) tW Minimum Reset Pulse Width Minimum Reset Removal Time ns ns tREM ns (*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) Measured with respect to carry out line. 5/11 HCF4022B TYPICAL APPLICATIONS DIVIDE BY N COUNTER(N DECODED OUTPUTS When the Nth decoded output is reached (N th clock pulse) the S-R flip-flop (constructed from two NOR gates of the HCF4001B) generates a reset pulse which clears the HCF4022B to its zero count. At this time, if the Nth decoded output is greater than or equal to 6, the COUT line goes high to clock the next HCF4022B counter section. The "0" decoded output also goes high at this time. Coincidence of the clock low and decoded "0" output high resets the S-R flip-flop to enable the HCF4022B. If the Nth decoded output is less than 6, the COUT line will not go high and, therefore, cannot be used. In this case "0" decoded output may be used to perform the clocking function for the next counter. < 10) WITH TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50) 6/11 HCF4022B WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2 : MINIMUM SETUP TIME (CLOCK INHIBIT TO CLOCK) (f=1MHz; 50% duty cycle) 7/11 HCF4022B WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50% duty cycle) WAVEFORM 4 : MINIMUM SETUP TIME (CLOCK TO CLOCK INHIBIT) (f=1MHz; 50% duty cycle) 8/11 HCF4022B Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 9/11 HCF4022B SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 10/11 HCF4022B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 11/11 |
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